The present invention relates to the field of electronic circuits, and, more particularly, to a synchronous counter for electronic memories. Moreover, the invention relates to a fast synchronous counter for memories which is faster than conventional counters.
In an electronic memory, for example of the non-volatile type, the structures that make up the memory are formed to ensure a normal read cycle. This read cycle begins with a request stimulus (i.e., switching of the addressing lines) and ends with the extraction of the data related to the addressed memory location.
In view of their construction characteristics, these conventional memories are capable of performing only one reading process at a time. Furthermore, each read cycle is identical to every other in terms of response of the memory. In order to be able to provide an efficient read cycle whose outcome is certain, it is necessary to allow the entire propagation of the read stimuli to evolve completely and always in the same manner to be able to extract the data from the memory.
It is in fact not possible to produce a new read stimulus before a preceding activation has ended without a resultant xe2x80x9cpenaltyxe2x80x9d of interrupting and suppressing the previously started process. In practice, the second read process overlaps the first one, cancels it, and replaces it. Accordingly, a read cycle for a memory of a conventional type is penalized by long read times for each read cycle. Each read cycle has the same duration as all other read cycles.
The overall duration of a read cycle is given by the sum of elementary signal propagation times, and in particular: address transition request detection (signal ATD); identification of the memory location to be read (addressing); selection of the paths for access to the location to be read (word line, bit line); pre-charging of the data lines (PC); evaluation of the responses of the individual memory cells by a sense amplifier; and transfer of the read data to the output analysis time memories (buffer).
The read times for each read cycle remain unchanged even if the new location to be read is adjacent to a location read in the directly preceding cycle. In this case it would be advantageous to be able to utilize the fact that the new read occurs in a position which is physically close to the preceding read position to provide increased read speed.
Moreover, the need to manufacture electronic memories whose functionality is guaranteed requires subjecting the memories to tests of various kinds. Among these tests, it is important to be able to verify the correct operation of the counter by a dedicated line. Conventional memories do not allow for monitoring the counter from outside thereof due to the carry propagation time.
An object of the present invention is to provide a synchronous counter for electronic memories which may be used with memories of the interleaved type and thus may be synchronized with an external control signal for reading the memory.
Another object of the present invention is to provide a synchronous counter for electronic memories whose configuration may be defined substantially immediately from outside the counter at each count start.
Still another object of the present invention is to provide a synchronous counter for electronic memories which may be updated internally during counting.
Yet another object of the present invention is to provide a synchronous counter for electronic memories which is substantially functionally insensitive to external stimuli during counting.
A further object of the present invention is to provide a synchronous counter for electronic memories whose functionality may be monitored from outside the memory without requiring additional circuits.
Still another object of the present invention is to provide a synchronous counter for electronic memories which is protected against unwanted loading of addresses which are not expressly intended for the memory.
Yet another object of the present invention is to provide a synchronous counter for electronic memories which allows for assignment of the maximum possible time for carry calculation, maximizing the operating frequency.
A further object of the present invention is to provide a synchronous counter for electronic memories in which the corresponding control signals are not simultaneously active.
Another object of the present invention is to provide a synchronous counter for electronic memories which is highly reliable and relatively easy to manufacture at competitive costs.
These objects and others, which will become apparent hereinafter, are provided by a memory counter circuit that includes a plurality of mutually connected counter stages, an internal address bus interfaced with each one of the counter stages for sending an external address signal to each one of the counter stages, and a circuit or means for loading the external address signal onto the internal address bus. The memory counter may further include an enabling circuit or means for enabling the connection between the internal bus and each one of the counter stages. This enabling means may be driven by a true address latch enable signal. Furthermore, the memory counter may also include a circuit or means for generating the true address latch enable signal starting from an external address latch signal and a fast address latch enable signal. The fast address latch enable signal may be adapted to drive the means for loading the external address onto the internal address bus. Additionally, a signal generation circuit for generating clock signals for synchronizing each one of the counter stages is also included. The synchronization signals are preferably not simultaneously active.